Beside outdoor leisure activities, quite some indoor time is spend on engineering related challenges. Educated in electronics engineering and with a nearly 40 years long career in development and management of integrated electronics, it is tempting to try out things which have been impossible to allocate time for in busy days at the office.
So, after many years use of ready made complex and immensely expensive commercial Computer Aided Design (CAD) software tools, it is fun – and at the same time an intellectual challenge – trying to create your own tools from scratch, obviously in very lean and simplified versions – you know, it has to be fun !
A challenge like this requires for me dusting off computer programming skills learned 3-4 decades ago and gaining insight in relevant algorithms. With some experience in ‘old-school’ programming languages like Fortran, Basic and Pascal, it was quite surprising but a real pleasure finding a modern, open source and actively maintained cross-platform Integrated Development Environment (IDE) named Lazarus based on (Delphi-) Pascal.
With this Rapid Application Development (RAD) tool available for free and many good tutorials and examples, it was straightforward to start developing a CAD application. The choice of application appeared to be an event driven digital circuit simulation tool and the name given was eLogSim.
After around a development time of one year, eLogSim became available for free as open source (under GPL license) at Sourceforge. The most noteworthy technical features of this application are it’s availability on several platforms (Windows 10 and various Linux flavors on two h/w platforms amd64 and arm/aarch64) and the statistical fault simulation capability built-in.
In the video below, the very basic functionality of eLogSim is briefly demonstrated. To dig further, download eLogSim and try out one or more of the many circuit examples provided.
In the works ..
Another application under development is ePnR. ePnR is a so-called Integrated Circuit standard cell placement & routing tool intended for small to medium size circuit layouts.
ePnR can read a SPICE like circuit netlist and along with a library describing available standard cells, place and route the circuit according to a chosen IC technology. An example of ePnR in action, is an adder for two 64 bit numbers. First screenshot shows a pre-placed version of the circuit comprising the relevant standard cells (green blocks) along with flight-lines depicting cell interconnects:
After pre-placement, ePnR can optimize placement of the standard cells for minimum, accumulated wire-length and then convert the black flight-lines to layout technology-correct horizontal & vertical wiring:
ePnR may finally export the resulting layout to an IC layout editor for further use. ePnR is of course open-source and licensed under GPL v3. Further information about ePnR and download options are available on Sourceforge.
A third application using the Lazarus IDE is currently in the works. If you use a GPS tracker e.g. an app on your smart phone during trekking, biking or skiing, it will in most cases be possible to store your track waypoints and elevation data as a GPX file. Having this at hand, an application calculating and displaying details on your track and graphically plotting the track in perspective 3D is viable. Such an application named eGPXviewer is currently in development. A glimpse of what it can do right now is:
and a 3D perspective view of the same track:
The latest release of the application may be found and downloaded at Sourceforge.